As I was presenting a poster I couldn’t skive the whole conference, so I spent quite a lot of Tuesday listening to presentations. Still managed to get out in the morning for an hour or two, and there was an organized tour of the castle in the evening.

Since this episode is a bit dull maybe it’s a good time to talk about the conference. The two most interesting talks I saw were from Altera and Xilinx. On different days, presumably to avoid a fight. The Altera talk was my favourite, although I don’t really have any experience of Altera’s FPGAs. Talk was by Vaughn Betz, probably better known in FOSS land as the author of the VPR place and route tool. The subject was the problems and opportunities of FPGAs on <40nm processes. The primary argument seems to be that smaller process sizes favour FPGAs over ASICs (traditionally better for performance and volume price). Primarily because doing an ASIC at 40nm costs upwards of $4m for a mask set (and you're going to make mistakes...), plus the physics gets messy when the feature size is smaller than the wavelength of the light used to manufacture them, so you'll need some very experienced engineers. Thus most ASIC users are stuck at ~130nm, whereas FPGA users get many of the speed and density benefits of a 40nm process with a fraction of the NRE costs.

The Xilinx talk was along similar lines, but seemed more of a marketing presentation for their latest range of devices. Weirdly enough the speaker got a standing ovation at the end. Academics coveting industrial sponsorship? (The speaker was quite a well-known senior engineer and retiring.)

Poster session went OK. Quite a lot of people read it (or at least looked at it for >30s). A few talked to me about it, one guy quite in depth! Felt relieved when it was over.

Anyway, on to the obligatory photos!