December 22nd, 2013
I went for another adventure today from Farnham Common near Slough to West Drayton just inside the M25. You might recall I’ve been roughly this way on several previous adventures. A really nice sunny day despite the pessimistic weather forecast.
A lot of the photos below are from Stoke Common a really lovely area of boggy grassland north east of Slough. I’ve been here several times and always enjoyed walking through it. Definitely worth visiting if you live in the area.
Near the end of the trip, just inside the M25, I had to take a less pleasant detour around a sewage works as a vital foot bridge over the canal had been inconsiderately demolished.
December 16th, 2013
This evening I went running for exactly 41 minutes 41 seconds and 41 hundredths of a second.
December 16th, 2013
Ah, the humble can of compressed air: is there any problem it can’t solve? Just now with his sidekick Henry he managed to repair my dead CPU fan!
December 15th, 2013
Almost a year since I released the last one, there’s a new lander-0.6.5.tar.gz package available. Nothing exciting: just fixing bit rot and some FreeBSD build fixes Dmitry Marakasov. Glad someone’s using it!
December 14th, 2013
I saw some pretty red berries when I was out adventuring near Marlow today. Probably highly toxic.
Really lovely winter morning today: cold and a sunny and muddy. I saw a robin which must mean it’s nearly Christmas!
November 30th, 2013
I Went exploring in Wantage, Oxfordshire today. It’s a nice little market town that’s apparently the birth place of Alfred the Great.
The local museum was unexpectedly brilliant. My favourite bit was this replica of a Wantage tram carriage complete with dead mice:
Predictably everything hereabouts is named after Alfred. Here’s King Alfred’s school which is a rather attractive building:
Afterwards I went for a semi-circular walk back to Didcot through the Lambourn Downs and Ridgeway that I’ve visited before. I stopped for lunch here by this huge hill.
November 24th, 2013
I recently added a code coverage option to the VHDL compiler, nvc, I’m working on. I tend to find code coverage a really useful tool when I’m writing RTL, especially the sort of control-dominated designs I do in my day job. I find Modelsim’s HTML coverage reports a bit frustrating so I’m trying to do something more user-friendly in my simulator.
If you elaborate your design with the
--cover option the generated code will be annotated to gather the following kinds of coverage:
- Statement – A counter is added for each executable statement in the design. A statement must be executed at least once to be “covered”.
- Branch – A branch is covered if it is both taken and not-taken at least once during execution
- Condition – A condition here is a Boolean sub-expression of branch test and it is covered by evaluating to both TRUE and FALSE at least once. For example
if A and B then contains one branch but two sub-conditions.
After a run with coverage enabled the statistics are automatically reported:
** Note: coverage report generated in /tmp/work/WORK.TEST.cover/
282/289 statements covered
71/94 branches covered
85/108 conditions covered
A HTML report is then generated which contains a top-level summary and a detailed report for each source file:
You can mouse over a non-covered branch or condition to get a hint as to why it was not covered.
The implementation is currently a work-in-progress but functions well enough for light usage. The biggest limitation at the moment is that the report only contains aggregated statistics per-file rather than per-instance statistics.
October 30th, 2013
Walking from Henley to Oxford has been something I wanted to try for ages, so having a day off this Tuesday I thought I’d give it a go. It’s about 25 or so miles if you take the scenic route. Unfortunately I think this should have been a summer project as despite setting off at 8am I ran out of day light around 5:30 a few miles short in a village called Marsh Baldon and had to escape via a well-timed bus. I’ll blame the amount of debris from Monday’s storm for slowing me down.
Some photos from epic adventure below:
October 30th, 2013
Sometimes the single week programmes are on iPlayer is a little too short:
(On this. Really good documentary BTW, no hurry to watch it…)
October 27th, 2013
I’ve spent a lot of time recently improving the waveform output of my VHDL compiler / simulator. Previously only the simple VCD format was supported: this only allows Verilog-style 4-value logic types to be dumped so doesn’t map very well onto VHDL types. The implementation was also very inefficient resulting in a 3-4x slowdown in simulation speed.
After experimenting with LXT for a while, NVC now uses GtkWave’s FST format by default. With some help from GtkWave’s author it can now dump full 9-value logic as well as most common VHDL types (enumerations, strings, integers, etc.).
I’ve put some work into improving the performance of waveform output and now dumping every signal to a FST incurs around 30% overhead. The VCD dumper has also been rewritten giving around 90% overhead. This format should generally be avoided unless you do not have access to GtkWave.
The screen shot below shows some of the new features: