I’ve been dogfooding my VHDL compiler for a project at work and now that it’s gotten to the point where it can simulate non-trivial designs, compile times are becoming significant. Especially when files use Xilinx primitives as the
vcomponents library takes a while to load.
At the moment I’m re-analysing every source file for each change I make, so obviously an improvement would be to write a makefile and only re-analyse the files that have changed and those that depend on them (e.g. an architecture must be re-analysed if the corresponding entity changed). But figuring out and maintaining the dependencies by hand is tedious and error prone so I’ve written a makefile generator that recursively finds the dependencies for previously analysed or elaborated units in a library. Invoke it like this:
nvc --make my_top_level >Makefile
make will do the minimum amount of work to rebuild all the out of date files. If the argument to
--make is an elaborated design then two convenience targets
wave will be added to run the simulation and run with waveform output respectively.
The code is fairly compact: only 400 or so lines of C.
This also turned out to be handy for solving a long-standing problem of not being able to bootstrap the standard and IEEE libraries with parallel make (
make -j). Previously the dependencies in the automake input file were incomplete, but now these are generated automatically by a
gen-deps target. The output (e.g. here) is then mangled with sed and committed into the git repository (this solves a chicken-and-egg problem where the
gen-deps target can only be run in an already built tree).