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Archives for 2011

Ominous Clouds

December 28th, 2011

Awesome sunset tonight in Hastings near my parents house. This is the local reservoir.

I followed Blodgett’s previous advice of using the spot metering mode and I also used the exposure compensation to make it a bit brighter. I’ve put loads more here but they’re mostly duplicates.

Winter Trees

December 27th, 2011

A forest missing its leaves somewhere near Marlow last week:

One advantage to having the trees in this state is that it’s much easier to see where you’re going when adventuring out in the wilderness…


December 10th, 2011

Today I walked from Farnham Common north of Slough on a meandering route into Yiewsley, West London. On the way I passed through Stoke Common which is a lovely bit of heathland that’s very rare here down south. I’ve actually been through here on a previous adventure last year. Also good are Langley Park and Black Park Country Park. Once inside the M25 however the scenery deteriorated pretty rapidly. Mind you, further up the Colne valley there is some pretty good walking. It was well cold though, which you can see from the frost still on the ground in the photos:

Sunny day

November 27th, 2011

Nice sunny day today unlike the past week which has been cloudy and miserable. Here’s a pleasant field near Marlow, Bucks. This footpath was apparently opened by no less than the Right Honourable Theresa May MP. I feel privileged to walk on it.

Here’s a picture of a seed pod thing. Maybe teasel. Experimenting with the aperture priority mode. Maybe overdone.

Dangerous Mushroom

November 27th, 2011

Here’s a weird looking mushroom I saw in Winchester yesterday:

Danger! Do not sample! Sample may cause DEATH.

Around Pangbourne

November 13th, 2011

Blodgett was querying whether November was a bit cold and dreary to go walking. Most assuredly not! This time of year is wonderful for walking. And not too cold as long as you go fast enough. Although you have to be careful not to get caught out in the dark.

Today I went for a wander around Pangbourne near Reading. Here’s a pretty church just across the Thames:

Here’s a llama, there’s a llama, and another little llama.

The woods look amazing this time of year. Such good colours!

Another good shaped tree this one. Maybe the lack of space restrictions makes it so pleasingly round?

Finally here are some nice spiky things I found. Not sure what they are.

Writing a VHDL compiler

November 5th, 2011

I haven’t posted much about any of my projects for a some time. This is because I’ve spent the past few months squirrelling away on something new: a while ago I decided a good way to learn more about VHDL would be to write a parser/checker for it. I had a vague plan of using it to write a linting tool or indexer. I’ve also wanted to learn more about LLVM so I started hacking together a code generator on the back end of the linting tool that generated LLVM IR for sequential VHDL processes. After that I thought I might as well write a simulation kernel too and it snowballed into something approximating an embryonic VHDL compiler/simulator.

The tool is currently called “nvc” which might stand for “Nick’s VHDL Compiler” or perhaps “New VHDL Compiler”. You can get it from GitHub here: github.com/nickg/nvc. See the README file for instructions on how to build and run it.

The eventual goal is full IEEE 1076-1993 support, or at least as much as possible until I get bored. Currently its capabilities are very limited. In particular it doesn’t implement enough of VHDL to compile the IEEE std_logic_1164 package which makes it almost useless for any real-world designs. The following should give an example of what it can do at the moment though.

entity counter is
    port (
        clk   : in bit;
        count : out integer );
end entity;
architecture behav of counter is
    process (clk) is
        variable count_var : integer := 0;
        if clk'event and clk = '1' then
            count_var := count_var + 1;
            count <= count_var;
        end if;
    end process;
end architecture;

This is a very simple behavioural model of a counter that increments on rising edges of clk. We can also add a top-level entity to generate the clock signal:

entity top is end entity;
architecture test of top is
    signal clk   : bit := '0';
    signal count : integer := 0;
    clkgen: process is
        wait for 5 ns;
        clk <= not clk;
    end process;
    uut: entity work.counter
        port map (
            clk   => clk,
            count => count );
    process (count) is
        report integer'image(count);
    end process;
end architecture;

The final process will print the value of the counter every time it changes. You may normally have written the clkgen process with a concurrent assignment:

clk <= not clk after 5 ns;

Unfortunately processes and instantiations and the only sort of concurrent statements implemented in nvc at the moment. This is not as restrictive as it sounds: apart from generate statements all others can be trivially rewritten as processes. This is in fact how they are specified in the standard.

First we need to run the analysis step which parses the code into an internal format, performs type checking, and runs some simplification passes such as constant folding. With the above code in a single file counter.vhd we can run:

$ nvc -a counter.vhd
[gc: freed 425 trees; 297 allocated]

The work library now contains the serialised abstract syntax tree for each analysed design unit:

$ ls -lh work
total 24K
-rw-r--r-- 1 nick nick    8 Nov  5 13:37 _NVC_LIB
-rw-r--r-- 1 nick nick  682 Nov  5 13:37 WORK.COUNTER
-rw-r--r-- 1 nick nick 1.6K Nov  5 13:37 WORK.COUNTER-BEHAV
-rw-r--r-- 1 nick nick   33 Nov  5 13:37 WORK.TOP
-rw-r--r-- 1 nick nick 7.6K Nov  5 13:37 WORK.TOP-TEST

Next we run the elaboration step which builds the full design hierarchy starting from a top level entity. It also runs the LLVM IR code generation step to produce a bitcode file.

$ nvc -e top

(This step produces a large amount of debug output which should be ignored.) If you look inside the work library again you should see the generated LLVM bitcode and a serialised AST for the elaborated design – this is used for debugging later.

$ ls -lhtr work | tail -2
-rw-r--r-- 1 nick nick 8.2K Nov  5 13:39 WORK.TOP.elab
-rw-r--r-- 1 nick nick 1.3K Nov  5 13:39 _WORK.TOP.elab.bc

The elaboration step runs a number of simple LLVM optimisation passes over the bitcode before writing it out but you can run more if you like using the standard LLVM opt tool.

Now we can finally simulate the model! The simplest way to do this is in batch mode as follows:

$ nvc -r --stop-time=50ns top
0ms+0: Report Note: 0
5ns+2: Report Note: 1
15ns+2: Report Note: 2
25ns+2: Report Note: 3
35ns+2: Report Note: 4
45ns+2: Report Note: 5

Normally nvc will run until there are no more events scheduled but as the clkgen process will schedule events forever we have to specify an explicit stop time. The bitcode file is transparently converted into native machine code using LLVM’s JIT engine when the simulation is loaded.

Commercial simulators usually provide an interactive debugging environment as well as a batch mode and nvc tries to emulate this. Use the -c switch to the run command to enter interactive mode:

$ nvc -r -c top

This mode uses TCL for command processing, which is the de-facto standard for scripting in the EDA industry. If you have readline or libedit installed you’ll also get fancy line-editing capabilities. The features here are currently pretty limited but we can see the state of all the signals in the design:

% show signals
:top(test):clk                STD.STANDARD.BIT         '0'
:top(test):count              STD.STANDARD.INTEGER     0

Note that nvc has collapsed the ports in counter with the signals in top as they are identical: this might be confusing if you’re searching for a particular name. Now we can run the simulation and verify the signal values change:

% run 45 ns
% 0ms+0: Report Note: 0
5ns+2: Report Note: 1
15ns+2: Report Note: 2
25ns+2: Report Note: 3
35ns+2: Report Note: 4
45ns+2: Report Note: 5
% show signals
:top(test):clk                STD.STANDARD.BIT         '1'
:top(test):count              STD.STANDARD.INTEGER     5

Notice that the run command returns straight away and the print outs happen in the background: this is because the interactive mode forks off another process to run the simulation.

A legacy of the project’s origins as a linter, the error messages try to be more helpful than most VHDL compilers:

counter.vhd:33: no suitable overload for operator 
"+"(STD.STANDARD.BIT, universal integer)
            clk <= not (clk + 1);

This is about the limit of what nvc can do at the moment. I’m not sure how far I’ll develop it but it’s been good fun hacking thus far. So obviously don’t start using it for real designs or reporting bugs just yet ;-).


October 30th, 2011

I spent last week in the US on a business trip. We were staying in the Westborough area which is really isn’t a very exciting place to be, especially if you don’t have a car. However I stayed in Boston on Friday night and spent Saturday doing some fast-paced sightseeing. The results of which you can see below.

The first set of photos are from the Cambridge area which isn’t strictly Boston but adjoined. This has got Harvard and MIT in it which are very pleasant to walk around. Also good is the MIT musem which has a LISP machine on display – but I’m not allowed to post photos.

After that we did the “freedom trail” which is a ~3 mile painted line around the city which takes you past all the historical landmarks. It’s actually quite a good idea, otherwise you’re a bit lost not knowing what to see.

America is a strange place though so I’m quite glad to be back home in England.


October 16th, 2011

Cows. On their own they’re placid enough but it’s a bit unnerving to encounter an autonomous column of them marching down a narrow lane.

Where are they going? And why? Bringing up the rear was a man who might have been a farmer but who was controlling who? I reckon the cows might have been exerting powerful MIND CONTROL.

Later on, having narrowly avoided enslavement to the cow legion, I found this nice statue hidden in a wood near Mapledurham.

Pylons! They are so awesome. This one idling in a field somewhere near Pangbourne.

Now it is Autumn

October 9th, 2011

It doesn’t seem very long since this blog declared that it was officially Spring. Now the weather has sorted itself out it is very much Autumn. I went out for a walk in the hills today, roughly here:

Here are some suspiciously friendly horses near the start:

The weather was a bit grey but I think that’s preferable to the weird heatwave we had last weekend.

This is a village called Turville which may seem strangely familiar as it’s often appeared on TV and films as Generic English Village. Most notably in the Vicar of Dibley. Given that, it’s surprisingly hard to find somewhere to take a decent picture of it. I’ve never ventured this far north into Buckinghamshire so this is all pretty new and exciting for me.

This amazing machine is the NOMMER4000: the latest in harvesting technology. It drives around a field gobbling up everything, digests it, and then spews it out of its spout into the accompanying truck. So voracious is its appetite that it doesn’t stop eating when the truck is full: instead the farmer just brings in a fresh empty one.

Green and pleasant land and what not. This is a village called Fingest. Has a weird shaped church.